A Case Study of Hierarchical Diagnosis for Core-Based SoC

In this paper, a silicon debug case study was given in the context of a hierarchical diagnosis flow for core-based SoC. We discuss (1) how to design a simple core wrapper that supports at-speed test, (2) how to map the failures collected from the chip level to core level, and (3) how to perform failure analysis and silicon debug under the guidance of diagnosis results. Terminology and Introduction The terminology used in this paper is briefly discussed below. SoC: Designs that integrate a complete system onto one chip are called System-on-a-Chip (SoC) designs. Core: In SoC designs, the design process involves an IC that is often made up of large pre-defined and preverified reusable building blocks or intellectual property (IP) blocks, such as digital logic, processors, memories, analog and mixed signal circuits. The IC building blocks are called cores or embedded cores Core Wrapper Design The IEEE 1500 core wrapper [8] is illustrated in (1) Wrapper Serial Port (WSP) has a set of serial terminals that could be sourced from chip-level pins or from an embedded controller such as an IEEE 1149.1-based (JTAG) controller. The WSP is used to load and unload instructions and data into and out of the IEEE 1500 registers. In addition to the wrapper serial input (WSI) and wrapper serial output (WSO) terminals shown i